Memory devices are in common use in a wide variety of applications. For example, memory devices are used in personal computers, telephone answering machines, and cellular telephones. Various types of memory devices are commercially available, including read-only memories ("ROMs"), which may be programmable ("PROMs"), and random access memories ("RAMs"), which may be either static random access memories ("SRAMs") or dynamic random access memories ("DRAMs"). Furthermore, there are a variety of DRAM types available, and more being developed. For example, asynchronous DRAMs, synchronous DRAMs ("SDRAMs"), and video graphics DRAMs are currently available, and Synchronous Link DRAMs (SLDRAMs) and RAMBUS DRAMs ("RDRAMs") will soon be available.
Although the following discussion of problems encountered when testing conventional memory devices will focus on such problems in the context of an SDRAM, it will be understood that these or similar problems exist to varying degrees with other types of memory devices. Similarly, although the solutions to these problems using the disclosed embodiments of the invention are explained in the context of an SDRAM, it will be understood that they are applicable to other types of memory devices.
One example of a conventional SDRAM 10 exhibiting problems that can be alleviated using the disclosed embodiments of the invention is shown in FIG. 1. The SDRAM 10 includes an address register 12 that receives either a row address or a column address on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). A row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory banks 20, 22 depending upon the state of a bank address bit BA forming part of the row address. Associated with each of the memory banks 20, 22 are a respective row address latch 30 which, stores the row address, and a row decoder 32, which applies various row signals to its respective array 20 or 22 as a function of the stored row address. The row address multiplexer 18 also couples row addresses to the row address latches 30 for the purpose of refreshing the memory cells in the arrays 20, 22. The row addresses are generated for refresh purposes by a refresh counter 40, which is controlled by a refresh controller 42.
After the row address has been applied to the address register 12 and stored in one of the row address latches 30, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 50. Depending on the operating mode of the SDRAM 10, the column address is either coupled through a burst counter 52 to a column address buffer 56 or to the burst counter 52 which applies a sequence of column addresses to the column address buffer 56 starting at the column address output by the address register 12. In either case, the column address buffer 56 applies a column address to a column decoder 58, which applies various column signals to respective column circuitry 60, 62, each of which includes sense amplifiers and associated circuitry.
The column circuitry 60, 62 receive data from the arrays 20, 22, respectively, and couple the data to a data output register 70, which applies the data to a data bus 72. Data to be written to one of the arrays 20, 22 is coupled from the data bus 72 through a data input register 74 to the column circuitry 60, 62 where it is transferred to one of the arrays 20, 22, respectively. A mask register 76 may be used to selectively alter the flow of data into and out of the column circuitry 60, 62 such as by selectively masking data to be read from the arrays 20, 22, respectively.
The above-described operation of the SDRAM 10 is controlled by a command decoder 78 responsive to high level command signals received on a control bus 79. These high level command signals, which are typically generated by a memory controller (not shown in FIG. 1), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the "*" designating the signal as active low. However, other high level command signals may be used. In either case, the command decoder 78 generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals.
The SDRAM 10 also includes an internal voltage regulator 80 that supplies various regulated voltages, including V.sub.PP, V.sub.CCR1 and V.sub.CCR2. V.sub.PP is typically a "pumped" voltage having a magnitude greater than the magnitude of an external supply voltage V.sub.CCX, and is used for such purposes as generating wordline voltages for the arrays 20, 22, and supplying power to the data output register 70. However, a negative pumped voltage V.sub.BB may also be generated that is used to bias the substrate of the SDRAM 10. The voltage V.sub.CCR1 is typically a regulated voltage that is used to apply power to the arrays 20, 22, and V.sub.CCR2 is typically a regulated voltage that is used to apply power to the other circuitry in the SDRAM 10.
The internal voltage regulator 80 is illustrated in further detail in FIG. 2. The voltage regulator 80 includes three internal voltage regulator circuits 90, 92, 94, each of which is powered by the external power supply voltage V.sub.CCX. The voltage regulator circuits 90, 92, 94 are identical to each other, and thus have the same performance characteristics. Each of the voltage regulator circuits 90, 92, 94 is also coupled to a reference voltage generator 96, which supplies the voltage regulator circuits 90, 92, 94 with a common reference voltage V.sub.REF. The design of the reference voltage circuit 96, which has the characteristics described below, is well within the ability of one of ordinary skill in the art. Therefore, in the interests of brevity, a specific design for the reference voltage circuit 96 will not be described.
The voltage regulator circuit 90 generates a regulated voltage V.sub.CCR1 which, as explained above, supplies power to the arrays 20, 22. Similarly, the voltage regulator circuit 92 generates a regulated voltage V.sub.CCR2, which supplies power to the other circuitry in the SDRAM 10. Finally, the voltage regulator circuit 94 generates a regulated voltage V.sub.CCR3, which supplies power to conventional charge pumps 98. The charge pumps 98, which are generally entirely separate circuits (not shown) for each pumped supply voltage, generate a positive pumped supply voltage V.sub.PP, which may be used as described above, and a negative voltage V.sub.BB, which, as described above, is used to bias the substrate of the SDRAM 10.
The performance characteristic of the regulator circuits 90, 92, 94 is shown in FIG. 3, in which the regulated output voltage V.sub.CCR is shown on the y-axis as a function of the external supply voltage V.sub.CCX plotted on the x-axis. As shown in FIG. 3, the regulated output voltage V.sub.CCR increases linearly with the external supply voltage V.sub.CCX until the regulator circuits 90, 92, 94 begin to regulate, which occurs at about two volts. Thereafter, the regulated output voltage V.sub.CCR remains constant as the external supply voltage V.sub.CCX continues to increase. However, the regulator circuits 90, 92, 94 are only capable of regulating the output voltage V.sub.CCR over a limited range of supply voltages. When the external supply voltage V.sub.CCX reaches about 4 volts, the output voltage from the regulator circuits 90, 92, 94 starts to increase linearly with V.sub.CCX in order to perform stress testing. Also, even if the regulator circuits 90, 92, 94 are capable of regulating when the external supply voltage V.sub.CCX is above 4 volts, they may still perform as illustrated in FIG. 3 if the reference voltage V.sub.REF increases with the external supply voltage V.sub.CCX when the external supply voltage V.sub.CCX is above 4 volts.
The performance characteristics of the regulator circuits 90, 92, 94 do not present a problem during normal operation of the SDRAM 10 because the external supply voltage V.sub.CCX is normally maintained within the operating range of the regulator circuits 90, 92, 94. However, these performance characteristics do present a problem during testing of the SDRAM 10, as explained below.
Difficulties also arise in testing the SDRAM 10 at external supply voltages V.sub.CCX above the normal operating range of the regulator circuits 90, 92, 94. More particularly, since the pumped voltage V.sub.PP is normally a voltage greater than, and directly proportional to, the regulated output voltage V.sub.CCR3 supplying power to the charge pumps 98, the voltages present in the charge pumps 98 can become very large as the regulated output voltage V.sub.CCR3 increases. Although the other regulated output voltages V.sub.CCR1 and V.sub.CCR2 are normally proportional to the external supply voltage V.sub.CCX above the normal operating range of the regulator circuits 90, 92, 94, the voltages present in the circuitry powered by the output voltages V.sub.CCR1 and V.sub.CCR2 are relatively low since V.sub.CCR1 and V.sub.CCR2 are typically less than V.sub.CCX. As the external supply voltage V.sub.CCX is increased above the normal operating range of the regulator circuits 90, 92, 94, the resulting high voltages present in the charge pumps 98, which may be 2-3 times the magnitude of the supply voltage, can damage the charge pumps 98, even though the arrays 20, 22 and other circuitry in the SDRAM 10 would continue to operate. As a result of the performance characteristics of the regulator circuits 90, 92, 94, it can be impractical to stress test the SDRAM 10 at adequately high external supply voltages V.sub.CCX.
The regulator circuits 90, 92, 94 have been described as generating output voltages V.sub.CCR1, V.sub.CCR2 and V.sub.CCR3 having the same magnitude. However, it will be understood that the problems described above would continue to exist even if the regulator circuits 90, 92, 94 were adjusted to output regulated output voltages V.sub.CCR1, V.sub.CCR2 and V.sub.CCR3 having different magnitudes or some of the regulated output voltages V.sub.CCR1, V.sub.CCR2 and V.sub.CCR3 were scaled to a lower voltage. For example, assume the regulator circuit 90 generates an output voltage V.sub.CCR1 of 1.5 volts and the regulator circuit 94 generates an output voltage V.sub.CCR3 of 3 volts when an external supply voltage V.sub.CCX within the normal operating range of the regulator circuits 90, 92, 94 is applied to the SDRAM 10, When the external supply voltage V.sub.CCX is raised 1 volt above the normal operating range, the regulator circuit 90 would generate an output voltage V.sub.CCR1 of 2.5 volts and the regulator circuit 94 would generate an output voltage V.sub.CCR3 of 4 volts. This regulated voltage V.sub.CCR3 of 4 volts might very well damage the charge pumps 98 even though the arrays 20, 22 would continue to operate without damage at a regulated output voltage V.sub.CCR1 of 2.5 volts.
There is therefore a need for an improved method and apparatus for supplying regulated voltages to the components of memory devices, including the SDRAM 10 and other varieties of DRAMs.